As semiconductor technology advances to narrower or smaller technology nodes, transistors used in semiconductor technology are gradually undergoing transition from planar complementary metal-oxide semiconductor (CMOS) transistors to three dimensional field-effect fin transistors (FinFETs). In a FinFET, the channel may be controlled from both sides of the gate structure. An improved ability to control the channel can thus be implemented in a FinFET compared to a MOSFET or CMOS transistor. A FinFET can suppress short channel effect fairly well. Compared to other related devices, FinFETs have better compatibility with current integrated circuit (IC) fabrication processes.
A fabrication process to form an existing N-type FinFET is shown in FIGS. 1-4. First, as shown in FIGS. 1-2, a semiconductor substrate 10 is provided. The semiconductor substrate 10 includes fin structures 11.
Specifically, the semiconductor substrate 10 includes a silicon substrate 101 with at least two separated protrusion structures and an insulating layer 102 between the protrusion structures. The insulating layer 102 is positioned to be lower than the protrusion structures. The protrusion structures, positioned to be higher than the insulating layer 102, are the fin structures 11.
Further, a gate structure 12 across the fin structures 11 is formed. The gate structure includes a gate oxide layer 121 and a gate electrode layer 122 on the gate oxide layer 121.
Further, a first spacer material layer 13′ is formed on the semiconductor substrate 10, the top and the sidewalls of the fin structures 11, and the top and the sidewalls of the gate structure 12. The first spacer material layer 13′ includes a silicon dioxide layer (not shown) and a silicon nitride layer (not shown) on the silicon dioxide layer.
Further, referring to FIG. 2, a lightly doped drain (LDD) ion implantation and a Halo ion implantation are performed on the fin structures 11 on both sides of the gate structure 12. A thermal annealing process is further performed to form an LDD ion implantation region and a Halo ion implantation region in the fin structures 11 on both sides of the gate structure 12.
Further, referring to FIG. 3, after the LDD ion implantation regions and the Halo ion implantation regions are formed, a second spacer material layer (now shown) is formed on the first spacer material layer 13′. The second spacer material layer is made of silicon nitride.
Further, a recess etching process is performed on the first spacer material layer 13′ and the second spacer material layer to form gate spacers (not shown) surrounding the gate structure 12 and fin spacers surrounding fin structures 11.
A fin spacer includes a silicon dioxide spacer 13a and a silicon nitride spacer 14a on the silicon dioxide spacer 13a. The silicon nitride spacer 14 is formed from the silicon nitride layer in the first spacer material layer 13′ and the silicon nitride layer in the second spacer material layer.
Further, referring to FIG. 3, an in-situ doping growth process is performed to form a silicon carbide layer 15 on the fin structures 11. The silicon carbide layer 15 is doped with the ions for forming the source and the drain of the FinFET. The doped silicon carbide layer 15 forms the source and the drain of the N-type FinFET. The ions, for forming the source and the drain, are phosphorus ions.
Further, as shown in FIG. 4, an epitaxial deposition is used to grow a silicon cap (Si-Cap) layer 16 on the silicon carbide layer 15. Further, a metal layer is formed on the Si-Cap layer and an annealing process is performed on the metal layer. The metal layer and the Si-Cap layer are melted to form a metal silicide layer (not shown).
Thus, an N-type FinFET can be formed. However, the performance of the N-type FinFETs formed by such existing fabrication process may still need to be improved. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.